1. Field of the Invention
This invention relates to the field of data recording and detecting schemes.
2. Background Art
In computer systems, information is stored on magnetic storage systems such as Winchester type hard disks or floppy disks. Data is stored in a series of spiral or concentric rings known as "tracks". The data consists of streams of transitions of polarity of magnetic particles on the disk surface. A number of schemes are used to detect these transitions and data.
One prior art data detection method is a peak detection system. A disadvantage of peak detection schemes is limited data density. Another prior art data detection scheme is known as partial-response class IV (PR-IV) signaling. Systems using PR-IV schemes can achieve higher recording density than the conventional peak detection systems.
In PR-IV systems, input signals are sampled before performing symbol sequence detection. An example of a prior art PR-IV decoder is illustrated in FIG. 1. An input signal is coupled to one terminal of switch 101. The other terminal of switch 101 is coupled to node 102. Node 102 is coupled as an input to symbol sequence detector 103. The output 104 of symbol sequence detector 103 is decoded data. Node 102 is also coupled to a timing recovery circuit indicated by dashed line 105. Timing recovery circuit 105 is comprised of phase detector 106, loop filter 108 and VCO 110. Node 102 is coupled as an input to phase detector 106. The output 107 of phase detector 106 is coupled as an input to loop filter 108. Loop filter 108 provides an output 109 to VCO 110. The output 111 of VCO 110 is a sampling clock signal that controls switch 101.
The timing recovery circuit 105 is required to adjust the clock signal for the sampler so that frequency drifts between oscillators in the send and receive circuits can be compensated for. This timing recovery circuit is typically a phase-locked loop (PLL) consisting of a sampled-data phase detector. The phase detector determines the phase error between the input signal and a VCO by computing the timing gradient from the sampled data values. Timing recovery is described in K. H. Mueller and M. Muller, "Timing Recovery in Digital Synchronous Data Receivers", IEEE Trans. Commun., vol. COM-24, pp. 516-530, May, 1976.
For PR-IV systems, phase error .DELTA..tau. can be determined by: EQU .DELTA..tau.=y.sub.n *X.sub.n-1 +y.sub.n-1 *X.sub.n ( 1)
where y.sub.n is the input sample value at time nT, x.sub.n is the quantized decision value of y.sub.n and T is the clock period of the system symbol rate. In a PR-IV system, x.sub.n can have a value of +1, 0, or -1.
A prior art system block diagram for implementing equation (1) is illustrated in FIG. 2. FIG. 2 is a phase detector for implementing a tracking mode. Input samples 200 are coupled to node 201. Node 201 is coupled to a delay 202. The output Y.sub.n of delay 202 is coupled to node 203. Node 203 is coupled to delay 204. Node 204 provides an output Y.sub.n -1 to multiplier 205. The output 206 of multiplier 205 is coupled to the noninverting input of summing node 207. The output 208 of summing node 207 is a phase error signal .DELTA..tau..
Node 201 is also coupled as an input of quantizer 209. Quantizer 209 provides an output 210 to delay 211. The output of delay 211 at node 212 is signal X.sub.n. X.sub.n is coupled as an input to delay 213 and as an input to multiplier 205. The output of delay 213, X.sub.n -1 is provided as an input to multiplier 214 along with Y.sub.n from node 203. The output 215 of multiplier 214 is coupled to the inverting input of summing node 207. In the embodiment illustrated, the transition curve of the quantizer has a range of -1, 0, and 1 for X.sub.n.
To assist the initial acquisition of the timing phase, a preamble sequence precedes the actual data. A commonly used preamble pattern for PR-IV has a received sample sequence {. . . -1, -1, +1, +1, -1, -1, +1, +1 . . . }such as illustrated in FIG. 3. FIG. 3 illustrates a PR-IV preamble pattern mapped as y versus time. The pattern provides alternating pairs of +1's and -1's. This pattern has the most number of transitions in a given period of time. However, a timing recovery scheme that only implements equation (1) often fails to acquire the correct timing. This simple scheme can falsely lock because a phase shift of T/2 will produce zero phase shift error. Therefore, a different algorithm is required during the acquisition phase.
A "variable threshold decision" (VTD) algorithm was proposed by F. Dolivo etc. in U.S. Pat. No. 4,890,299 entitled "Fast Timing Acquisition for Partial-Response Signaling", and "Fast Tinning Recovery for Partial-Response Signaling Systems", F. Dolivo, W. Schott, and G. Ungerbock, IEEE International Conference on Communications, June, 1989, pages 573-577. The VTD scheme forces the system to recognize the preamble pattern by reducing the number of thresholds in the quantizer to one and dynamically changing this threshold level based on the data received. This scheme is illustrated in FIG. 4.
FIG. 4 illustrates the prior art VDT algorithm for acquiring the PR-IV preamble pattern. Input samples 200 are provided to node 401. Node 401 is coupled to delay 202. The output of delay of 202 is signal Y.sub.n at node 203. Y.sub.n is coupled as an input to delay 204 and to multiplier 214. The output of multiplier 204 is signal Y.sub.n -1 and is provided as an input to multiplier 205 along with signal X.sub.n from node 212. The output 206 of multiplier 205 is provided as input to the non-inverting input of summer 207. The output of summer 207 is phase error 208. Node 401 is also coupled to quantizer enclosed in block 404. The output 405 of quantizer 404 has a value of -1, 0 or 1 and is provided as an input to delay 211. The output of delay 211 at node 212 is signal X.sub.n. X.sub.n is provided as an input to delay 213 and as an input to multiplier 205.
The output of delay 213 is signal X.sub.n -1 at node 402. The signal is provided as an input to multiplier 214. The output 215 of multiplier 214 is coupled to the inverting input of summer 207. Node 402 is coupled to comparator 403 which is a sign (X) comparator. The output 408 of comparator 403 is coupled to the select input of switch 409. Signal +Vth'and signal -Vth'are coupled as inputs to multiplexer 409. The signal 408 selects between these inputs. The output 410 of multiplexer 409 is coupled to one terminal of multiplexers 411 and 412. The other input of multiplexer 411 is signal +Vth. The other input of multiplexer 412 is signal -Vth. A node select switch 413 is coupled to multiplexer 411 and 412 to select between the input signals. The output of multiplexer 411 is coupled to the inverting input of amplifier 406 of quantizer 404. The output of multiplexer 412 is coupled to the non-inverting input of amplifier 407. Node 401 is coupled to the non-inverting input of amplifier 406 and to the inverting input of amplifier 407.
The mode select signal 413 is set for either tracking or acquisition mode. In acquisition mode, multiplexers 411 and 412 are set to receive the input from multiplexer 409. The output of multiplexer 409 is set to either of +vth'and -Vth'. In the acquisition mode, the quantizer 404 receives the same input from the multiplexers 411 and 413, either +Vth'or -Vth'.
In the tracking mode, mode select switch sets multiplexer 411 to receive signal +Vth and sets multiplexer 412 to receive signal -Vth. The quantizer 404 thus receives different input signals from the respective multiplexers.
A disadvantage of the approach of FIG. 4 is that it requires several multiplexers to switch between-the thresholds, and the thresholds are different for the acquiring and tracking modes. Also, the quantizer architecture is different from well known architectures. Therefore, additional hardware is required to implement the VTD algorithm.